HR-DSSS PMD Operation

HR-DSSS PMD Operation
The operation of the HR-DSSS PMD translates the binary representation of the PPDUs into a
radio signal suitable for transmission. The HR-DSSS PMD is the same as DSSS PMD, except
for a different modulation type necessary to deliver higher data rates. For 1Mbps and 2Mbps,
the HR-DSSS PMD uses the Barker spreading sequence, which is the same for 802.11 DSSS
implementations. HR-DSSS uses CCK to provide the spreading sequences for the 5.5Mbps and
11Mbps data rates. The HR-DSSS PMD uses the channel plan shown in Table 5.1.
CCK uses an I/Q modulation architecture with a spreading code 8 chips long at a chipping rate
of 11 million chips per second. Each symbol (group of data bits) transmitted is represented by
a particular CCK spreading code. Each chip of the spreading code is complex—that is, it has
more than two possible phases. The spreading codes are known as complementary codes based
on Walsh/Hadamard functions. This formula represents the phase values for each of the spreading code chips represented as
c0 to c7. The minus sign for chips 4 and 7 provides a 180-degree rotation to optimize the
sequence correlation properties and minimize DC offsets.
For 5.5Mbps operation, CCK encodes four data bits (d0 to d3) per symbol onto the 8-chip
spreading code. Data bits d2 and d3 encode the basic symbol as shown in Table 5.2. This
encoding table satisfies the phase 2, 3, and 4 values show in the previous formula.  CCK uses data bits d0 and d1 (as shown in Table 5.3) to encode the phase 1 term in the previous
formula, using DQPSK to further encode the chips and obtain the actual spreading code.
Thus, every other symbol is given an extra 180-degree rotation. This overall modulation provides
nearly orthogonal spreading codes, which significantly improves the capability of the
radio signal to survive multipath distortion and RF interference For 11Mbps operation, Table 5.3 also provides the phase 1 value for the spreading code formula.
Table 5.4 provides the phase values for the remaining data bits, based on QPSK, according
to these dibit/phase value assignments:
d2, d3—phase 2 value
d4, d5—phase 3 value
d6, d7—phase 4 value
Thus, the overall process modulates eight data bits onto each 8-chip spreading code.