DSSS Spreading Sequence

DSSS Spreading Sequence
The general idea of direct sequence is to spread digitally the baseband data frame (PPDU) first,
then modulate the spread data to a particular frequency. Figure 5.9 illustrates typical components
of a DSSS transmitter.  The transmitter spreads the PPDU by combining the PPDU with a pseudo-noise (PN) code
(sometimes referred to as a chip or spreading sequence) via the binary adder. The PN sequence
for direct sequence systems consists of a series of positive and negative 1s (ones). The specific
PN code for 802.11 DSSS is the following 11-chip Barker sequence, with the leftmost bit
applied first to the PPDU:
+1, -1, +1, +1, -1, +1, +1, +1, -1, -1, -1
The output of the binary adder is a DSSS signal having a higher rate signal than the original
data signal. A 1Mbps PPDU at the input, for example, will result in an 11Mbps spread signal
at the output of the adder. The modulator translates the baseband signal into an analog signal at
the operating transmit frequency of the chosen channel.
DSSS is different than Code Division Multiple Access (CDMA). CDMA operates in a similar
fashion; however, it uses multiple orthogonal spreading sequences to enable multiple users to
operate at the same frequency. The difference is that 802.11 DSSS always uses the same
spreading sequence, but it enables users to choose from multiple frequencies for concurrent
operation.
A figure of merit for DSSS systems is known as processing gain (sometimes called spreading
ratio), which is equal to the data rate of the spread DSSS signal divided by the data rate of the
initial PPDU. The minimum allowable processing gain is 10 within the U.S. and Japan, according
to applicable frequency regulatory agencies (FCC and MKK, respectively). To ensure compliance
and minimize potential signal interference, the IEEE 802.11 standard minimum
processing gain requirement is set at 11.