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Once an ESD Event Occurs, Limit Discernable Effects

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Once an ESD Event Occurs, Limit Discernable Effects

Despite all efforts to the contrary, an ESD event may still occur. If it produces physical damage, little can be done in most cases except replacement of the affected component or the entire node. One of the few exceptions to this is the use of memory error detection and correction techniques, which can help identify and avoid permanently damaged memory elements; however, few other portions of a wireless sensor network node contain redundancy comparable to that found in a memory. So, generally, a node cannot automatically recover from a hardware failure.

The same is not true, though, for system upsets. The effects of a nondestructive ESD event are greatly affected by system firmware and software.[37] The analogy is to the engineering definitions of stress and strain: stress is the disturbing force; strain is the response of the system to the applied stress. In the case of ESD-resistant firmware and software design, stress is often the corruption of a register by an ESD event, and strain is how the system firmware and software respond to the incorrect register value. ESD-resistant firmware can reduce the consequences of ESD events, should they occur.

The design of ESD-resistant firmware and software is often done at increased cost, both in development time and in size of the implemented code. The code size is a particularly sensitive point, due to the large effect memory costs have on total network node cost. This cost must be balanced with the "mission-critical" nature of the wireless sensor network application (i.e., the effect losing a network node or having it perform an improper operation due to an ESD event will have on the overall application) and the cost of additional hardware efforts to reduce the rate of ESD events. Often it is less expensive to reduce or eliminate the effect of an ESD event than it is to eliminate the ESD event itself.

Register corruption can affect all parts of microcontroller operation. Corruption of data registers is an obvious problem. In addition, because the Program Counter is an internal register, it can be corrupted by an ESD event, leading to incorrect program flow. Finally, interrupt masks and other status information are also stored in internal registers; corruption of these can lead to improper behavior.

One of the basic tenets of ESD-resistant programming is to not trust the existing state of the microcontroller. Bits set or cleared at some time in the past may have become corrupted due to an ESD event. To protect against this possibility, the desired values should be restored immediately prior to their use, regardless of their present state. This minimizes the time during which the system is vulnerable to upset. Other techniques are specific to the type of information stored:

Boxleitner[38] has an excellent discussion on principles useful in ESD-resistant programming.

[21]Warren Boxleitner, Electrostatic Discharge and Electronic Equipment: A Practical Guide for Designing to Prevent ESD Problems. New York: IEEE Press. 1989.

[22]M. Mardiguian, ESD hardening of plastic housed equipment, EMC Test & Design, July/August 1994, pp. 21–24.

[23]Boxleitner, Electrostatic Discharge and Electronic Equipment.

[24]Ajith Amerasekera et al., Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulation, Proc. 34th Annu. IEEE Intl. Reliability Physics Symp., 1996, pp. 318–326.

[25]Ajith Amerasekera, Addressing ESD for microprocessors and ASICS in 21st-century technologies, Symp. on VLSI Circuits Dig. of Technical Papers, 2000, pp. 84–87.

[26]Amerasekera and Duvvury, ESD in Silicon Integrated Circuits.

[27]Charvaka Duvvury and Ajith Amerasekera, ESD: a pervasive reliability concern for IC technologies, Proc. IEEE, v. 81, n. 5, May 1993, pp. 690–702.

[28]Charvaka Duvvury, ESD protection device issues for IC designs, Proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 41–48.

[29]Charvaka Duvvury and Ajith Amerasekera, Advanced CMOS protection device trigger mechanisms during CDM, IEEE Trans. Components, Packaging, and Manufacturing Technology — Part C, v. 19, n. 3, July 1996, pp. 169–177.

[30]William D. Mack and Robert G. Meyer, Protecting BiCMOS circuits, EMC Test Design, July/August 1992, pp. 26–31.

[31]Amerasekera and Duvvury, ESD in Silicon Integrated Circuits. Chapter 9.

[32]Ke Gong et al., A study of parasitic effects of ESD protection on RF ICs, IEEE Trans. Microwave Theory and Techniques, v. 50, n. 1, January 2002, pp. 393–402.

[33]Frederic Stubbe et al., A CMOS RF-receiver front-end for 1 GHz applications, Symp. VLSI Circuits Dig. of Technical Papers, 1998, pp. 80–83.

[34]P. Leroux and M. Steyaert, High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection, Electronics Lett., v. 37, n. 7, 29 March 2001, pp. 467–469.

[35]Paul Leroux, Johan Janssens, and Michiel Steyaert, A 0.8-dB NF ESD-protected 9-mW CMOS LNA operating at 1.23 GHz [for GPS receiver], IEEE J. Solid-State Circuits, v. 37, n. 6, June 2002, pp. 760–765.

[36]Ming-Dou Ker et al., ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness, Proc. IEEE Radio Frequency Integrated Circuits Symp., 2002, pp. 427–430.

[37]Boxleitner, Electrostatic Discharge and Electronic Equipment.

[38]Ibid.

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