Reaching the Integrated Circuit
Protecting an integrated circuit from an electrostatic
discharge is difficult because the structures in an integrated circuit have very
limited power dissipation capabilities and overvoltage survival abilities. Once
a discharge reaches the package of an integrated circuit, however, it is likely
that the discharge has been weakened by both wide distribution and attenuation.
The integrated circuit designer has several design techniques available to
further attenuate the discharge and to design paths for the discharge to travel
away from sensitive circuits within the chip itself. There has been a great
amount written in the literature on ESD-resistant design of integrated circuits;
exemplary resources are Amerasekera et al.,[24] Amerasekera,[25] Amerasekera and Duvvury,[26] Duvvury and
Amerasekera,[27] and
Duvvury.[28]
The first step in integrated circuit protection is to employ
structures at the pads of the chip to protect internal circuits from incoming
ESD discharges. Protection structures are widely used for both CMOS[29] and BiCMOS[30] integrated circuits, although
their design necessarily changes greatly with the minimum feature size and other
details of the fabrication process.[31] Generally, however, pad-level ESD protection is
usually accomplished by the same impedance-control methods used at the circuit
board level. These impedance-control methods provide low shunt impedances to the
Vdd or Vss supply of the circuits to which the pads are
connected, while providing high series impedances on the signal lines leading to
the protected circuits. For digital input and output pads, the series impedance
is often just a series resistor. The mechanism by which the low impedance to the
Vdd or Vss supply is generated can vary greatly, from
passive systems such as integrated capacitors and diodes, to relatively
sophisticated active circuits that detect the high incoming ESD voltage (or
current), then couple the signal pad to one of the Vdd or
Vss supplies for the duration of the event. The design of ESD
protection circuits is nontrivial because the circuits must survive the ESD
event themselves, and most circuit modeling software does not adequately model
the behavior of semiconductor devices at
the extreme levels of voltage and current commonly encountered during a
discharge. As the minimum feature size of integrated devices shrinks with
improving lithographic techniques, circuit devices become more sensitive to the
effects of ESD, and the design of their associated ESD protection systems
becomes more difficult. One advantage of small-geometry processes, however, is
that their switching devices can be fast; this can be useful in some active
protection circuit designs if the devices are not directly exposed to the ESD
event itself.
The second step in ESD protection is to protect the supplies of
the integrated circuit. ESD supply protection circuits are two-terminal
structures that generally have the dual role of reverse-voltage protection, so
that Vss does not exceed Vdd by a significant amount, and
forward-voltage clamping, so that Vdd does not rise so high relative
to Vss that damage may occur. The final protection scheme is
illustrated in Exhibit
4.
The design of ESD protection structures is made still more
difficult when it is desired to protect RF, instead of digital, signal pads.
Because the purpose of such pads is to pass high-frequency energy, and the
circuit impedance is relatively low, it is usually not possible to place fixed
resistors in series with them without affecting their performance. Further, the
parasitic capacitance associated with most ESD protection circuits often
provides an unacceptably low impedance path to the Vdd or
Vss supplies for the desired signal, even when the circuit is not
active. The parasitic capacitance is often high due to the size of the ESD
protection circuit required to ensure that it can pass the discharge current
safely, without damage occuring, and that its resistance is low enough to avoid
the generation of an IR drop sufficient to damage the protected circuit. In
addition, the ESD protection structure
itself can degrade the noise figure of low-noise amplifiers, due to capacitive
coupling to noise present in the substrate or to noise generated within the
protection structure itself.[32]
Nevertheless, it is possible to achieve a level of ESD protection
to RF pads. One approach is to incorporate the parasitic capacitance of the ESD
protection structure as part of the impedance matching structure of the RF
circuit, and to employ needed matching components for ESD protection.[33] An example of this is the use
of the series matching inductor in a CMOS low noise amplifier as the series
input impedance element providing ESD protection to the circuit.[34], [35] Recently, a 900-MHz receiver
that survives 8-kV Human Body Model (HBM) ESD events has been reported.[36]
An additional level of complexity arises when systems-on-a-chip
(SoCs) are considered. For EMC reasons, SoCs often employ several multiple
Vdd and Vss supply pins, each supplying specific circuits.
For example, the supplies for analog and digital circuits are often separated,
and supplied from separate pins on the integrated circuit. It then becomes
necessary to place additional integrated ESD supply protection circuits between
the supplies. The resulting system is illustrated in Exhibit 5. An important consideration
when such multiple-supply systems are used is to ensure that the
supply-to-supply ESD protection structures will not conduct under all possible
conditions of operation (short of an actual ESD event, of course), and for all
possible variations in the supply voltages. For example, suppose Vdd2
is nominally 2.0 V, generated by a switching voltage converter from
Vdd1, supplied by removable primary battery, with a nominal voltage
of 1.5 V. Further, assume that the ESD supply protection structure between the
two supplies is a simple reverse-biased diode. Under normal operation,
Vdd1 is always less than Vdd2, so no current is drawn by
the protection structure; however, when a battery is first inserted in an
inactive device, Vdd1 immediately appears, although Vdd2
is still at or near zero volts because the voltage converter has not yet become
active. This can result in a very large current being drawn by the now
forward-biased ESD protection structure. Under these conditions, an anomalous
high current spike will occur when the battery is inserted. In the best-case
scenario, this current does not cause damage to the protection structure, and
the spike ends when the voltage of Vdd2 rises to the level needed to
reverse-bias the ESD protection structure again. In the worst-case scenario, the
current spike is large enough to cause the terminal voltage of the battery to
drop significantly (due to the nonzero ESR of the battery). The terminal voltage
may drop far enough, in fact, that the voltage converter will be unable to
generate its nominal 2.0 V, latching the node in this undesirable state. Often,
the exit from this inoperative but battery-draining state occurs when the ESD
protection device fails in an open circuit; alternatively, the battery may
quickly discharge. The problem of undesired conduction can also occur at a temperature extreme, if Vdd1 and
Vdd2 have significantly different temperature coefficients. In this
example, the problem could be prevented by placing not one, but three series
diodes in the ESD supply protection circuit. With three diodes, the 1.5 V of the
replaced battery is insufficient to cause conduction of the ESD supply
protection circuit. It also means that the ESD supply protection circuit between
Vdd1 and Vdd2 does not begin to protect the
Vdd1 supply during an ESD event until Vdd1 rises above the
Vdd2 voltage plus three forward diode voltage drops, or about four
volts in this example. Until then, the Vdd1 supply pin must be
protected by the ESD supply protection circuit to Vss1. Whether or
not this is sufficient depends on the integrated circuit technology and type of
discharge at hand; but for these and other reasons, ESD supply protection
circuits more sophisticated than a simple reverse-biased diode are often used in
modern integrated circuit designs.
Exhibit 5: Mixed-Signal IC Protection
An additional point that is often overlooked in ESD
protection is the assignment of signals to package pins (or pads, in the case of
ball grid arrays [BGAs] and other pinless integrated circuit packages). In
practice, ESD events on integrated circuits tend to strike the corner pins most
often because they are the most exposed. On BGAs, the outer row of pads, and
especially the corner pads on the outer row, are the most exposed. One may take
advantage of this effect and assign the most sensitive signal lines, such as
those leading to RF and analog inputs and other minimally protectable CMOS
gates, to pins or pads in the center of the package. In the case of RF input
pins, this approach has the added benefit of (usually) minimizing the length of
input wire bonds, providing the minimum possible parasitic package inductance
and, therefore, the minimum variation in the input impedance match associated
with manufacturing variations of bond wire length
Sections
