Once Inside, Design Paths for the Discharge to Travel
Once Inside, Design Paths for the Discharge to Travel
If, despite the best efforts of the designer, the discharge
arrives on the circuit board, one is in a significantly more difficult position.
the charge will want to redistribute on all metal it can reach; however, it
still obeys Ohm's law, and the most current and the least voltage will develop
across the lowest impedance. Thus, one must steer the ESD current pulse down a
low impedance path that avoids sensitive components. Because the discharge is a
high-frequency event, one should consider the impedance at high frequency of
paths leading from the point of entry of the discharge. The electrostatic
discharge, which has major spectral components above 1 GHz, will tend to avoid
series inductance and will capacitively couple very easily.
With this behavior in mind, several circuit board layout design
features can increase protection of integrated circuits:
-
Use wide and short Vdd and Vss circuit
board runners to integrated circuits. Keep these runners close to each other,
for maximum capacitance. This design method produces low-impedance structures
that encourage more of the discharge energy to remain on the circuit board, and
less to travel inside the integrated circuit. In addition, wide, short runners
produce smaller voltage drops when large ESD currents pass through them. This
reduces the likelihood of voltage upset. Finally, it minimizes the area and,
therefore, the radiation efficiency of any high-frequency current loop resulting
from an ESD event.
-
Place Vdd and Vss decoupling
capacitors close to their integrated circuit, with wide, short connections. This
policy allows the discharge to reach the Vdd and Vss pins
of the integrated circuit nearly simultaneously, resulting in little or no change in their voltage differential.
This reduces the likelihood of voltage upset.
-
Place RC networks on sensitive digital inputs. Series
R-shunt C networks can protect sensitive digital inputs of integrated circuits,
by making the entry into the integrated circuit a higher impedance path than an
alternative on the circuit board. The series resistor should be placed as close
to the integrated circuit as possible, to reduce the possibility that the
discharge may travel around the resistor by another path and still enter the
integrated circuit. The shunt capacitor should be placed as close as possible to
the point of discharge entry onto the input runner, so that the discharge is
controlled as early as possible in its path on the circuit board.
-
Make circuit board runners to external connector contacts as
narrow as possible. This includes the ground runner to the connector. Narrow
runners have high series inductance and, therefore, higher impedance to a
high-frequency ESD event.
-
Consider the use of diodes between digital signal lines and
both Vdd and Vss to clamp the voltage swing possible on
the signal lines during an ESD event. Keep in mind, however, that, many times,
the diode switching time is too slow to be effective, and that the real
mechanism at work is likely to be the diode capacitance, which acts as a bypass
to carry the discharge current away from the integrated circuit. If an
experiment is performed and diodes are found to be successful, try replacing the
diodes with capacitors, which are usually smaller and cheaper.
-
Use care in the placement of "influential" microcontroller
runners, such as reset and interrupt request lines. Keep them away from the
edges of circuit boards and other ESD entry points, such as housing openings.
Small capacitors from the influential runners to Vdd and/or
Vss can be used to bypass electrostatic discharges. When multilayer
circuit boards are used, runners may also be buried on their inner layers.
-
Keep high-impedance circuits away from ESD entry points.
High-impedance circuits are the circuits most susceptible to ESD charge
injection. An example is the microcontroller clock circuit. The impedance of the
crystal oscillator circuit may be 106 Ohms or more; a small amount of
charge placed there can be sufficient to upset the circuit.
-
Keep voltage management and voltage or current references
away from ESD entry points. Many times, ESD failures result not from the
corruption of signal lines, but from corruption of the references to which they
are compared. This frequently happens in the case of external analog sensors
using an internal analog-to-digital converter. Corruption of the voltage
reference used by the analog-to-digital converter is just as damaging as
corruption of the sensor data itself.
-
Consider spark gaps for troublesome entry paths. Spark gaps,
or field effect structures, can be used to encourage electrostatic discharges to
follow desired paths. These structures, which are sharp shapes of circuit board
metalization, can produce low-impedance paths for high-voltage signals, while
remaining high-impedance paths for low-voltage signals. These can be helpful in
particularly difficult ESD situations, such as those involving external
connectors and other direct connections from the outside to integrated circuits.
They should be placed as close as possible to the discharge source. Other nearby
metal runners and edges, associated with undesired ESD paths, should be as round
and smooth as possible.
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