THE EFFECTS OF ESD ON ICS

THE EFFECTS OF ESD ON ICS

Generally, ESD can damage an IC in two ways: thermal effects due to the energy of the discharge applied to the small geometries of active devices or interconnects, and overvoltage effects, in which a MOS gate or other dielectric may break down. Additional information on damage mechanisms may be found in Amerasekera et al.,^[7] Amerasekera and Duvvury,^[8] and Duvvury and Amerasekera.^[9]

The AC current density during an ESD event may be large enough to cause metal vaporization, resulting in metalization opens and circuit failure. Many ESD events can produce sufficient heating to melt the silicon of active devices, a feature exacerbated by the fact that the resistivity of silicon drops as it is heated. A section of an active device that begins to overheat decreases its resistance, encouraging more current to flow through that section, increasing the heating still further until failure occurs.

In addition to catastrophic device failures, an ESD event may degrade semiconductor junctions by the introduction of traps. These traps are a source of noise, and can raise the noise figure of RF devices. In wireless sensor network nodes, this is most troubling when an antenna (a large, easy target) is hit by an ESD discharge, which travels to the RF amplifier and may damage the RF amplifier transistor. Such effects can be immediate, or they can produce latent defects that may appear after weeks or months of operation.

The AC voltages present during an ESD event may cause dielectric breakdown of the gate oxide of MOS devices. As the minimum feature size of CMOS devices is reduced, the gate oxide thickness of the devices is also reduced, making them increasingly susceptible to this effect.

In addition to physical damage, an ESD event can result in system upset. One way in which this can occur is by the inversion of supply voltages. A positive discharge onto a "ground" plane may raise the potential of V_ss far above V_dd. A similar effect occurs with a negative discharge onto a V_dd circuit board runner. These events, of course, usually inhibit proper IC operation during the ESD event, and may have lasting effects afterward due to the loss of system state information. This can be caused, for example, by the loss of the microcomputer program counter value or activation of a system power-on reset. Similar effects can occur due to a discharge to the microcomputer reset line itself; unlike V_ss and V_dd, it is not necessary for the reset line to exceed the supply rails to cause an upset — a simple change of logical state (e.g., momentarily transitioning from a logical "1" to a logical "0") is all that is required. For this reason, the protection of internal reset lines is key to producing an ESD-resistant design.^[10]

Because RAM operates by stored charge on integrated capacitors, it is sensitive to ESD events, and RAM memory values may be partially or completely erased by them. Note that it is possible to have memory erasures without an actual air discharge; the presence of a strong electric field is sufficient to change the charge on RAM cells.