EMC-Aware Layout Procedure
EMC-Aware Layout Procedure
When modifying an existing design, with components of known
characteristics and systems of known performance, it is usually not necessary to
make an exhaustive EMC analysis; however, when starting a new design, possibly
in a new market, incorporating a new transceiver and maybe new sensors, it is
wise to have a structured approach to component placement and layout. A
successful strategy has been to employ the organized signals concept,[15] which, although originally
designed to optimally arrange pins in a connector for minimum cross talk, can be
applied more generally:
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The first step is to list all potential threats and victims
present in the design. This list can be drawn from the preceding discussion,
plus any signals or components particular to the design that are known to have
caused problems in the past.
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From this list, identify the greatest potential threat and
the greatest potential victim. Usually the greatest potential threats will be
the reactive elements of switching voltage converters, loop filter capacitors
associated with integrated bus clock synthesizers, and the Vdd and
Vss pins of all CMOS integrated circuits. The greatest potential
victim is usually the receiving antenna, due to its size, but perform the
analysis on each design. For capacitive coupling, high-impedance nodes tend to
be victims and low-impedance nodes threats; for inductive coupling,
low-impedance nodes tend to be victims and high-impedance nodes threats. The
evaluation of potential threats is the area in which an engineer's judgment most
comes into play; general principles, similar to the preceding principles, can be
stated, but there truly is no substitute for experience.
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The next step is to floor plan the product so that the
greatest potential threat and the greatest potential victim are as far apart as
possible, given the additional constraints of desired product size and shape.
This minimizes both inductive and capacitive coupling. If multiple circuit
boards are to be used in the design (e.g., if a separate plug-in sensor board is
to be used), do not forget that the boards will be mated together, and that one
should think three-dimensionally.
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The following step is to return to the threats and victims
list, and select the greatest potential threat and the greatest potential victim
from those components remaining on the list. Those components are then placed on
the floor plan. The process then repeats until the list is empty. If an unequal
number of threats and victims exist, the last remaining victim is used for the
remaining threats (and vice-versa). In the highly integrated designs common to
wireless sensor network nodes, the organized signals process is usually a short
one because often, only two or three potential victims (the antenna and a
sensor), and relatively few threats (voltage converters and oscillators)
exist.
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The next step in the EMC-aware layout procedure is to place
components and circuit board traces so that the area of the return current loops
of EMC-relevant circuits are minimized. This minimizes inductive coupling.
Prominent circuits and components to consider here are the reactive elements and
filter capacitors of switching voltage converters, loop filter capacitors
associated with integrated bus clock synthesizers, and the bypass capacitors on
the Vdd and Vss pins of all CMOS integrated circuits. Do
not place all return currents on a single "ground" plane; follow the current
from each source to each load and back to the source, and ensure that that loop
is as small as the component geometry and other design considerations can make
it.
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Next, minimize the length of circuit board runners carrying
high-frequency signals. Prominent among these are the external buses, both
serial and parallel, including any connections to external memory. This
minimizes possible capacitive coupling.
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Next (if not done so already as part of an earlier step),
separate the current loops for high current loads from those of other circuits.
Of principal concern here are any large currents going to actuators, sensors, or
user interface items that may switch on and off. These loops should be separated
from those of other circuits, joined only at the terminals of the power source.
This minimizes possible conducted coupling.
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Finally, if any connectors are used in the design, employ
the organized signals concept to assign signals to the pins in a manner that
will minimize cross talk.
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