The External Interface
An old aphorism states, "If you try to please everyone, no
one will like it," and nowhere is this more true than in the design of an
external transducer interface. The manufacturer must put enough flexibility in
the interface to meet the needs of a large segment of the market, without adding
so much to the node that it becomes economically prohibitive to use in any one
application.
To start, the manufacturer
must decide if the transducer interface is to be analog or digital. The output
of most sensor elements is inherently analog, while the wireless sensor network
transmits only digital data; therefore, an analog-to-digital conversion must
take place. Similarly, many actuators produce an analog output;
digital-to-analog conversion is therefore necessary. Placing analog-to-digital
and digital-to-analog converters (ADCs and DACs) on the network node may reduce
the total cost of the system, especially if multiple sensors are attached to
each node and the converters can be shared between them. Converters of more than
moderate speed, accuracy, and precision are difficult to manufacture on a
conventional digital IC process, however, and add power consumption and die area
(and, therefore, cost). A manufacturer of wireless sensor network nodes may
choose to reduce the cost of the product by incorporating neither ADCs nor DACs,
instead using a digital transducer interface. This requires the user to employ
transducers that have internal (or inherent) ADCs and DACs, which may
significantly limit the market of this network node design.
If the decision is to employ a digital transducer interface, the
next decision is to decide if the interface will be a completely logical one, or
if special-purpose outputs (essentially very large pad drivers, used as
switches, etc.) will be included. The addition of special-purpose outputs may
make the network node capable of stand-alone operation in some high-volume but
low-margin applications (e.g., a wireless light switch), by eliminating the need
for a second, special-purpose switching transistor in the system design. A node
with special-purpose outputs also may be capable of satisfying some low-volume
but high-margin applications (e.g., military sensing). The special-purpose
outputs can greatly increase the size of the integrated circuit, however,
driving up costs for those applications that do not use them. The manufacturer
must decide which market is to be addressed.
One compromise is to place a purely logical interface on the
network node IC, but place a second, special-purpose die controlled by the
logical interface, in the same package. In this way, the network node IC may be
produced in high volume, while one of several relatively cheap (and easy to
design and fabricate) special-purpose chips may be mated to it as the
application requires. This approach offers market flexibility at the cost of
making multiple special-purpose chips, and the cost associated with placing
multiple chips in the same package. A variation on this theme is employed by
thin-film ceramic module manufacturers, which may use the same network node IC,
but customize each design by modifying the surrounding components as needed for
the application.
If the manufacturer decides that the transducer interface is to be
a completely logical one, decisions must still be made. The first decision is whether the interface should be in series or
parallel. This decision hinges on the relative value in the implementation of
speed versus size.
A parallel interface (an external bus) has the advantage of speed;
with eight data pins, a byte (eight bits) can be transmitted in each clock
cycle. Alternatively, at the same data rate, an eight-bit parallel interface may
be clocked at one-eighth the clock rate of a serial interface; this may be an
advantage if the interface is a source of RF interference. (However, the larger
number of circuit board traces used by a parallel interface may negate this
advantage.) If the network node contains a microcontroller, the
microcontroller's general-purpose input/output (GPIO) pins can be efficiently
used in a parallel interface. In addition, sensors designed for an eight-bit
microcontroller bus can be quite common; however, these benefits come at some
cost. The parallel interface requires ten pins on the network node (eight data
pins, one clock, and one control or enable pin), which also must be routed to
the sensor(s). In very small implementations, routing these lines may be
difficult, or require a more expensive multilayer circuit board. In very low-end
applications, especially those in which a custom integrated circuit (as opposed
to an off-the-shelf microcontroller) is used, the ten pins needed for the sensor
interface may double the pin count of the chip. Although the extra pins alone
will drive up the product cost (due to the cost of wire bonding and packaging),
the die area of the chip may now be pad-limited (i.e., determined by the number
of wire bonding pads needed around its periphery, instead of by the area of the
integrated circuits themselves). This will establish a lower limit on the size
of the chip, regardless of the fabrication process employed.
A serial interface has the advantage of size. With a single data
pin (plus one each for the clock and the control or enable pin), a serial
interface is small, with a minimal effect on both chip pad count and circuit
board area. This makes it ideal for very small, low-cost products, although it
also has its drawbacks. Because the serial interface trades speed for size, it
is slower; a careful analysis should be done to ensure that sufficient data can
be transferred across it under worst-case conditions. These can occur, for
example, in an emergency condition, when the wireless sensor network is
requesting frequent sensor updates or giving frequent commands to an actuator.
Several types of serial interfaces are also available on the market, not all of
which are compatible. This can be a serious problem when field-replaceable
transducers are replaced by those from a different vendor. Often, the interfaces
may appear to be compatible, but may differ in some detail, such as implied
addressing (i.e., their behavior when sequential data packets are sent to the
same address). In addition, some serial interfaces are proprietary. To avoid
these issues, many transducer manufacturers do not manufacture products with
serial interfaces; this limits the market of a serial-interface wireless sensor
network node (unless an external series-to-parallel converter is employed). Another alternative
is the use of a mixed-mode interface, such as pulse-width modulation. Neither
fully analog nor fully digital, pulse-width modulation encodes the transferred
data in the duty cycle of a square wave.
Once the series/parallel interface decision is made, the remaining
issue is one of selecting speeds and standards. Speeds, when not set by the
standard, are usually limited by power, electromagnetic compatibility (EMC), and
the application requirements.
Leakage current aside, the power consumed by a switching circuit
element is
where
-
P = the power consumed by the
switching element (in W)
-
C = the capacitance of the element (in
F)
-
V = the voltage range over which the
element is switching (in V)
-
f = the frequency of the switching (in
Hz)
Because the voltage term is squared, a voltage reduction has the
greatest effect on power consumption of an interface. However, to be compatible
with industry (i.e., available transducers), the selection of available voltages
is limited to a few choices: 2.7 V, 1.8 V, or, in a few cases, 1.0 V. The
capacitance is typically unknown to the chip designer. Because the transducer to
be used is typically not known (unless the chip is being designed for a specific
transducer), its load capacitance is also not known; to make matters worse, the
capacitance of the interface lines between the chip and the transducer, which
can be significant (several tens of picofarads), is unknown as well.
This leaves the frequency of operation as the only parameter
over which the designer has significant control. To minimize both power
consumption and the potential for the production of electromagnetic interference
(see Chapter 9),
the designer typically will attempt to minimize the required maximum frequency
of operation of the interface, consistent with meeting application requirements.
The interface capacitance is unknown, therefore, the designer can only state a
maximum total capacitance that the chip will support (based on the size of the
driver circuit on the chip) and the maximum frequency of operation under that
condition.
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